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[Software Engineering] SDRAMController

Description: SDRAM Controller 设计详细文档 ，很有参考价值！-SDRAM Controller Design of detailed documentation, a good reference!
Platform: | Size: 446464 | Author: 王一 | Hits:

[VHDL-FPGA-Verilog] altera_sdram

Description: Simple SDRAM controller source code for Altera DE2 board
Platform: | Size: 7168 | Author: leblebitozu | Hits:

[Other] testbench

Description: ddr sdram controller datd module source code
Platform: | Size: 3072 | Author: KrishnaKishore | Hits:

[VHDL-FPGA-Verilog] altera_up_avalon_sram

Description: 基于Avalon的SDRAM控制器IP核-Avalon SRAM Controller
Platform: | Size: 320512 | Author: 涂登乾 | Hits:

[VHDL-FPGA-Verilog] ceshi0326

Description: 高速AD采集卡应用程序及SDRAM控制器-High-speed AD acquisition card applications and SDRAM controller
Platform: | Size: 38912 | Author: chaos | Hits:

[assembly language] sdramctrl2

Description: sdram controller in vhdl
Platform: | Size: 15360 | Author: jil | Hits:

[VHDL-FPGA-Verilog] IR_PEN

Description: infra pen controller, cmos sensor control and sdram control
Platform: | Size: 50176 | Author: byungchan | Hits:

[VHDL-FPGA-Verilog] DDRSDRAMControllerverilogcode

Description: 这个设计是使用Virtex-4实现DDR的控制器的，设计分为三个主要模块：Front-End FIFOs,DDR SDRAM Controller和Datapath Module。其中主要是DDR SDRAM Controller,当然还有测试模块。-This design is the use of Virtex-4 implementation of the DDR controller, the design is divided into three main modules: Front-End FIFOs, DDR SDRAM Controller and Datapath Module. Are one of the main DDR SDRAM Controller, of course, have the test module.
Platform: | Size: 477184 | Author: fdasfds | Hits:

[VHDL-FPGA-Verilog] sdram_vhd

Description: FPGA设计的SDRAM控制器，有仿真代码，已通过验证-FPGA Design of SDRAM controller, there is simulation code has been validated
Platform: | Size: 2186240 | Author: yuhl | Hits:

[VHDL-FPGA-Verilog] SDRAMHDL

Description: SDRAM基础性控制核 很有用的 VHDL状态机实现-SDRAM control of the nuclear basic useful VHDL state machine implementation
Platform: | Size: 12288 | Author: 王欢 | Hits:

[Windows Develop] mt48lc16m16a2

Description: SDram 接口verylog 程序 SDram 接口verylog 程序-SDram interface procedures verylog
Platform: | Size: 9216 | Author: lili | Hits:

[VHDL-FPGA-Verilog] tut_DE2_sdram_vhdl

Description: This tutorial explains how the SDRAM chip on ltera’s DE2 Development and Education board can be used with a Nios II system implemented by using the Altera SOPC Builder.
Platform: | Size: 546816 | Author: *Roma* | Hits:

[Linux-Unix] first_cpu

Description: nios ii cpu核，包含通用IO口、sdram、flash、uart-nios ii cpu、genernal io port、sdram、falsh、uart
Platform: | Size: 13319168 | Author: 陆yong | Hits:

[Other] sdram_vhdl_lattice

Description: sdram的控制程序，程序分为控制端口模块、时钟模块、数据传输模块及刷新等模块-sdram control procedures, process control port is divided into modules, clock modules, data transfer module and refresh modules
Platform: | Size: 369664 | Author: 邢雷 | Hits:

[Embeded-SCM Develop] hssdrc_latest

Description: SDRAM 控制器 Verilog实现，很有借鉴意义。-SDRAM controller core Verilog implementation。With good referential significance.
Platform: | Size: 424960 | Author: metallica | Hits:

[VHDL-FPGA-Verilog] SRAM_controller

Description: 对于想编写sdram控制器的人来说，值得借鉴-Sdram controller would like to prepare for the people, to learn
Platform: | Size: 157696 | Author: churchill | Hits:

[Documents] Memory

Description: 存储器类型介绍:SSRAM SDRAM Flash Memory EEPROM EPROM-Memory Introduction
Platform: | Size: 8192 | Author: Kim Zeng | Hits:

[Linux-Unix] Linux_bc

Description: 对vga接口做了详细的介绍，并且有一 ·三段式Verilog的IDE程序，但只有DMA ·电子密码锁，基于fpga实现，密码正 ·IIR、FIR、FFT各模块程序设计例程， ·基于逻辑工具的以太网开发，基于逻 ·自己写的一个测温元件（ds18b20）的 ·光纤通信中的SDH数据帧解析及提取的 ·VHDL Programming by Example（McGr ·这是CAN总线控制器的IP核，源码是由 ·FPGA设计的SDRAM控制器，有仿真代码 ·xilinx fpga 下的IDE控制器原代码, ·用verilog写的，基于查表法实现的LO ·精通verilog HDL语言编- up:in STD_LOGIC down:in STD_LOGIC run_stop:in STD_LOGIC wai_t: in std_logic_vector(2 downto 0) lift:in std_logic_vector(2 downto 0) ladd: out std_logic_vector(1 downto 0) ) end control
Platform: | Size: 18683904 | Author: liuzhou | Hits:

[VHDL-FPGA-Verilog] DDRSDRAM

Description: DDR SDRAM的veilog hdl程序，经过验证 效果不错-DDR SDRAM' s veilog hdl procedures, good results verified
Platform: | Size: 475136 | Author: 寒心雪林 | Hits:

[VHDL-FPGA-Verilog] 03.EDK8.2

Description: 使用xilinx virtex4芯片，设计环境为EDK，其中包含uart,片外sram操作，flash操作，DDR SDRAM操作，MAC自发自收，audio，video等试验-Xilinx virtex4 use chip design environment for the EDK, which contains the uart, chip sram operation, flash operation, DDR SDRAM operation, MAC spontaneous self-admission, audio, video and other tests
Platform: | Size: 22821888 | Author: 肖姗姗 | Hits:
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